MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 389
MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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16.5.5
This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART
module.
16.5.5.1
The UART module responds to reads with byte data. Reserved registers return zeros.
16.5.5.2
The UART module accepts write data as bytes. Write cycles to read-only or reserved registers complete
normally without exception processing, but data is ignored.
16.5.5.3
An internal interrupt request signal notifies the interrupt controller of any unmasked interrupt conditions.
The interrupt priority level is programmed in ICR2.
Freescale Semiconductor
USRn[RxRDY]
USRn[TxRDY]
Transmitter
Bus Operation
Receiver
Enabled
Enabled
Read Cycles
Write Cycles
Interrupt Acknowledge Cycles
internal
module
internal
module
select
select
RxD
TxD
UMR1n[PM] = 11
UMR1n[PT] = 1
UMR1n
UMR1n[PM] = 11
MCF5272 ColdFire
[PM] = 11
A/D
Figure 16-30. Multidrop Mode Timing Diagram
ADD 1
0
UMR1n[PT] = 0
ADD1
ADD1
®
A/D
A/D
Integrated Microprocessor User’s Manual, Rev. 3
C0
1
1
ADD 1
Peripheral Station
C0
C0
Master Station
A/D
A/D
Status Data
UMR1n[PT] = 2
(C0)
ADD 2
ADD2
ADD2
A/D
A/D
1
1
Status Data
(ADD 2)
A/D
0
UART Modules
16-29
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