MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 359
MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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15.3.5
TERs are used to report events recognized by the timer. On recognition of an event, the timer sets the
appropriate TERn bit, regardless of the corresponding interrupt enable bits (ORI and CE) in the TMRn.
Writing a 1 to a bit clears it; writing 0 has no effect. Both bits must be cleared before the timer can negate
the request to the interrupt controller. Both bits may be cleared simultaneously.
Table 15-2
Freescale Semiconductor
15–2
Bits
1
0
Reset
Field
Addr
R/W
Name
CAP
REF
—
describes TERn fields.
15
Timer Event Registers (TER0–TER3)
Reserved, should be cleared.
Output reference event.
0 The counter has not reached the TRR value
1 The counter reached the TRR value. TMR[ORI] is used to enable the interrupt request caused by this
Capture event.
0 The counter value has not been latched into the TCAP.
1 The counter value is latched in the TCAP. TMR[CE] is used to enable capture and the interrupt request
event. Write a 1 to this bit to clear the event condition.
caused by this event. Write a 1 to this bit to clear the event condition.
MCF5272 ColdFire
MBAR + 0x210 (TER0); 0x230 (TER1); 0x250 (TER2); 0x270 (TER3)
Figure 15-6. Timer Event Registers (TER0–TER3)
Table 15-2. TERn Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0000_0000_0000
—
Read/Write
Description
2
REF CAP
1
Timer Module
0
15-5
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