MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 55
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
0x026C
0x0270
0x0280
0x0284
0x0288
0x028C
0x0300
0x0304
0x0308
0x030C
0x0310
0x0314
0x0318
0x031C
0x0320
0x0328
0x032C
0x0330
0x0334
0x0338
0x033C
0x0340
0x0344
0x0348
MBAR
MBAR
Offset
Offset
Timer 3 Counter Register
Timer 3 Event Register
Watchdog Reset Reference Register
Watchdog Interrupt Reference Register
Watchdog Counter Register
Watchdog Event Register
Port0 B1 Data Receive
Port1 B1 Data Receive
Port2 B1 Data Receive
Port3 B1 Data Receive
Port0 B2 Data Receive
Port1 B2 Data Receive
Port2 B2 Data Receive
Port3 B2 Data Receive
Port0-3 D Data Receive
Port0 B1 Data Transmit
Port1 B1 Data Transmit
Port2 B1 Data Transmit
Port3 B1 Data Transmit
Port0 B2 Data Transmit
Port1 B2 Data Transmit
Port2 B2 Data Transmit
Port3 B2 Data Transmit
Port0-3 D Data Transmit
MCF5272 ColdFire
Table xiii. Timer Module Memory Map (continued)
Register Name
Register Name
Table xiv. PLIC Module Memory Map
®
Integrated Microprocessor User’s Manual, Rev. 3
TCN4
TER4
WRRR
WIRR
WCR
WER
PLRB10
PLRB11
PLRB12
PLRB13
PLRB20
PLRB21
PLRB22
PLRB23
PLRD0
PLRD1
PLRD2
PLRD3
PLTB10
PLTB11
PLTB12
PLTB13
PLTB20
PLTB21
PLTB22
PLTB23
PLTD0
PLTD1
PLTD2
PLTD3
Old Mnemonic
Old Mnemonic
TCN3
TER3
No change
No change
No change
No change
P0B1RR
P1B1RR
P2B1RR
P3B1RR
P0B2RR
P1B2RR
P2B2RR
P3B2RR
P0DRR
P1DRR
P2DRR
P3DRR
P0B1TR
P1B1TR
P2B1TR
P3B1TR
P0B2TR
P1B2TR
P2B2TR
P3B2TR
P0DTR
P1DTR
P2DTR
P3DTR
New Mnemonic
New Mnemonic
lv
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