MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 478

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

IEEE 1149.1 Test Access Port (JTAG)
21.4
The boundary scan register contains bits for all device signal and clock pins and associated control signals.
Bidirectional pins include a single scan bit for data (IO.Cell) as shown in
controlled by an enable cell, shown in
bidirectional pin is an input or an output. One or more bidirectional data bits can be serially connected to
a control bit as shown in
interpreted only after examining the I/O control bit to determine pin direction.
Open-drain bidirectional bits require separate input and output cells as no direction control is available
from which to determine signal direction. Programmable open-drain signals also have an enable cell
(XXX.de) to select whether the pin is open drain or push-pull. Signals with pull-up or pull-down resistors
have an associated enable cell (XXX.pu); one enable cell can control multiple resistors.
Figure 21-3
21-4
Data from
Boundary Scan Register
system
to
logic
Figure 21-8
1 = EXTEST, CLAMP, HI-Z
0 = Otherwise
MCF5272 ColdFire
Figure
show the four MCF5272 cell types.
G1
1
1
MUX
21-7. Note that when bidirectional data bits are sampled, bit data can be
Figure 21-3. Output Cell (O.Cell) (BC–1)
®
Figure
Integrated Microprocessor User’s Manual, Rev. 3
From last
Shift DR
cell
21-5. The control bit value determines whether the
G1
1
1
MUX
Clock DR
1 D
C1
Update DR
To next
cell
Figure
1 D
C1
21-6. These bits are
Freescale Semiconductor
To output
buffer