MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 347

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

14.5
The programming model for the QSPI consists of six registers. They are the QSPI mode register (QMR),
QSPI delay register (QDLYR), QSPI wrap register (QWR), QSPI interrupt register (QIR), QSPI address
register (QAR), and the QSPI data register (QDR).
There are a total of 80 bytes of memory used for transmit, receive, and control data. This memory is
accessed indirectly using QAR and QDR.
Registers and RAM are written and read by the CPU.
14.5.1
The QMR register, shown in
Parameters such as clock polarity and phase, baud rate, master mode operation, and transfer size are
determined by this register. The data output high impedance enable, DOHIE, controls the operation of
QSPI_Dout between data transfers. When DOHIE is cleared, QSPI_Dout is actively driven between
transfers. When DOHIE is set, QSPI_Dout assumes a high impedance state.
Table 14-3
Freescale Semiconductor
Bits
15
14
Address
Reset
Field
R/W
Programming Model
DOHIE
MSTR
Name
gives QMR field descriptions.
QSPI Mode Register (QMR)
MSTR DOHIE
Because the QSPI does not operate in slave mode, the master mode enable
bit, QMR[MSTR], must be set for the QSPI module to operate correctly.
15
Master mode enable.
0 Reserved, do not use.
1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.
Data output high impedance enable. Selects QSPI_Dout mode of operation.
0 Default value after reset. QSPI_Dout is actively driven between transfers.
1 QSPI_Dout is high impedance between transfers.
MCF5272 ColdFire
14
Figure
13
Figure 14-3. QSPI Mode Register (QMR)
Table 14-3. QMR Field Descriptions
BITS
14-3, determines the basic operating modes of the QSPI module.
®
Integrated Microprocessor User’s Manual, Rev. 3
10
0000_0001_0000_0100
NOTE
CPOL CPHA
MBAR + 0x00A0
9
R/W
Description
8
7
Queued Serial Peripheral Interface (QSPI) Module
BAUD
0
14-9