MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 121
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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5.3
Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The ColdFire
solution is to include a parallel output port providing encoded processor status and data to an external
development system. This port is partitioned into two 4-bit nibbles: one nibble allows the processor to
transmit processor status, (PST), and the other allows operand data to be displayed (debug data, DDATA).
The processor status may not be related to the current bus transfer.
External development systems can use PST outputs with an external image of the program to completely
track the dynamic execution path. This tracking is complicated by any change in flow, especially when
branch target address calculation is based on the contents of a program-visible register (variant
addressing). DDATA outputs can be configured to display the target address of such instructions in
sequential nibble increments across multiple processor clock cycles, as described in
Execution of Taken Branch (PST =
processor’s high-speed local bus to the external development system through PST[3:0] and DDATA[3:0].
The buffer captures branch target addresses and certain data values for eventual display on the DDATA
port, one nibble at a time starting with the least significant bit (lsb).
Execution speed is affected only when both storage elements contain valid data to be dumped to the
DDATA port. The core stalls until one FIFO entry is available.
Table 5-2
Freescale Semiconductor
Hex
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
PST[3:0]
Binary
0000
0001
0010
0011
0100
0101
0110
0111
Real-Time Trace Support
shows the encoding of these signals.
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more clock
cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
Begin execution of one instruction. For most instructions, this encoding signals the first clock cycle of an
instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions, generate
different encodings.
Reserved
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to enter
user mode.
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug and/or
performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to the
DDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is
signaled on the PST port, followed by the appropriate marker, and then the data transfer on the DDATA port.
Transfer length depends on the WDDATA operand size.
Begin execution of taken branch. For some opcodes, a branch target address may be displayed on DDATA
depending on the CSR settings. CSR also controls the number of address bytes displayed, indicated by the
PST marker value preceding the DDATA nibble that begins the data output. See
Execution of Taken Branch (PST =
Reserved
Begin execution of return from exception (RTE) instruction.
MCF5272 ColdFire
Table 5-2. Processor Status Encoding
0x5).” Two 32-bit storage elements form a FIFO buffer connecting the
®
Integrated Microprocessor User’s Manual, Rev. 3
0x5).”
Definition
Section 5.3.1, “Begin
Section 5.3.1, “Begin
Debug Support
5-3
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