MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 163
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.2.2
The supervisor-level MBAR,
internal peripherals. It is written with a MOVEC instruction using the CPU address 0xC0F. (See the
ColdFire Family Programmer’s Reference Manual.) MBAR can be read or written through the debug
module as a read/write register, as described in.” Once MBAR has been initialized, it can be read and
written in supervisor mode at the address programmed into the base address (BA) field.
The valid bit, MBAR[V], is cleared at system reset to prevent incorrect references before MBAR is
written; other MBAR bits are uninitialized at reset. To access internal peripherals, write MBAR with the
appropriate base address (BA) and set MBAR[V] after system reset.
All internal peripheral registers occupy a single relocatable memory block along 64-Kbyte boundaries. If
MBAR[V] is set, MBAR[BA] is compared to the upper 16 bits of the full 32-bit internal address to
Freescale Semiconductor
0x014–
MBAR
Offset
0x00C
0x01C
0x02C
0x03C
0x28C
0x000
0x004
0x008
0x010
0x020
0x024
0x028
0x030
0x034
0x038
0x280
0x284
0x288
Watchdog interrupt reference register (WIRR) [p. 6-12]
Module Base Address Register (MBAR)
Watchdog reset reference register (WRRR) [p. 6-12]
System configuration register (SCR) [p. 6-5]
Watchdog counter register (WCR) [p. 6-13]
Watchdog event register (WER) [p. 6-13]
[31:24]
MCF5272 ColdFire
Figure
Reserved
Module base address register (MBAR), after initialization [p. 6-3]
Programmable interrupt transition register (PITR) [p. 7-7]
Programmable interrupt wakeup register (PIWR) [p. 7-8]
6-2, specifies the base address and allowable access types for all
®
Integrated Microprocessor User’s Manual, Rev. 3
Power management register (PMR) [p. 6-7]
Device identification register (DIR) [p. 6-11]
Software Watchdog Registers
Interrupt Controller Registers
Table 6-1. SIM Registers
Interrupt control register 1 (ICR1) [p. 7-4]
Interrupt control register 2 (ICR2) [p. 7-5]
Interrupt control register 3 (ICR3) [p. 7-5]
Interrupt control register 4 (ICR4) [p. 7-5]
Reserved
Interrupt source register (ISR) [p. 7-6]
[23:16]
Reserved
Active low power register (ALPR) [p. 6-10]
System protection register (SPR) [p. 6-6]
[15:8]
Reserved
Reserved
Reserved
Reserved
System Integration Module (SIM)
vector register (PIVR) [p.
Programmable interrupt
[7:0]
7-9]
6-3
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