MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 533
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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G
GPIO
H
Halt, fault-on-fault,
Hardware
Hash table
I
Initialization sequence
Instruction cache
Instruction execution times,
Instruction set
Integer data formats,
Integer data formats in memory,
Integer data formats in registers,
Interrupt controller
Interrupts
J
JTAG
Freescale Semiconductor
overview,
port
Ethernet initialization,
Ethernet algotithm,
Ethernet,
interaction with other modules,
operation,
overview,
physical organization,
programming model,
reset,
fetch pipeline,
general summary,
MAC summary,
MAC unit execution times,
summary,
memory,
registers,
overview,
pending and mask registers, 7-4, 7-5, 7-5,
bus acknowledge cycles,
PLIC GCI,
request inputs,
BDM debug port,
boundary scan register,
IDCODE register,
instruction register,
overview,
control registers, 17-2,
data direction registers,
data registers,
4-10
2-11
11-33
2-10
17-1
4-7
2-15
7-1
21-1
4-8
13-10
2-2
19-23
17-11
3-4
5-16
21-2
2-13
6-11
2-9
11-8
21-7
4-12
4-7
11-33
21-4
MCF5272 ColdFire
20-19
17-8
17-10
2-24
3-4
2-11
2-10
4-8
7-5
®
Integrated Microprocessor User’s Manual, Rev. 3
L
Local memory
Loopback, Ethernet internal and external,
M
MAC
Matching
MBAR, 7-6,
Mechanical data
Memory
Memory maps
Memory, SIM register,
MII
Modules
MOVE instructions timing,
N
Non-IEEE 1149.1 operation,
O
Opcodes
Organization,
Output port command registers,
P
Parallel input/output ports,
restrictions,
TAP controller,
test access port,
module interactions,
registers,
data representation,
hardware support,
instruction execution timings,
instruction set summary,
operation,
programming model, 2-4,
programming modelProgramming models
buffering and impedance,
package dimensions,
pinout,
integer data formats,
list of tables,
USB,
serial management channel timing,
transmit signal timing,
base address register,
debug,
illegal handling,
MAC,
12-7
2-4
22-1
3-2
4-2
3-3
7-8
1-xl
21-8
A-1
21-3
21-2
2-3
2-3
3-4
4-1
2-11
22-2
6-2
2-9
23-18
1-6
3-4
2-20
B-1
2-7
21-8
16-18
3-4
23-20
11-8
Index-3
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