MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 18
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Paragraph
Number
9.1 Overview ........................................................................................................................................ 9-1
9.2 SDRAM Controller Signals ........................................................................................................... 9-1
9.3 Interface to SDRAM Devices ........................................................................................................ 9-4
9.4 SDRAM Banks, Page Hits, and Page Misses ................................................................................ 9-6
9.5 SDRAM Registers ......................................................................................................................... 9-6
9.6 Auto Initialization .......................................................................................................................... 9-9
9.7 Power-Down and Self-Refresh ...................................................................................................... 9-9
9.8 Performance ................................................................................................................................. 9-10
9.9 Solving Timing Issues with SDCR[INV] .................................................................................... 9-12
9.10 SDRAM Interface ...................................................................................................................... 9-14
10.1 DMA Data Transfer Types ......................................................................................................... 10-1
10.2 DMA Address Modes ................................................................................................................ 10-2
10.3 DMA Controller Registers ......................................................................................................... 10-2
11.1 Overview .................................................................................................................................... 11-1
11.2 Module Operation ...................................................................................................................... 11-1
11.3 Transceiver Connection ............................................................................................................. 11-3
11.4 FEC Frame Transmission ........................................................................................................... 11-4
xviii
9.5.1 SDRAM Configuration Register (SDCR) .......................................................................... 9-6
9.5.2 SDRAM Timing Register (SDTR) ..................................................................................... 9-8
9.10.1 SDRAM Read Accesses ................................................................................................. 9-15
9.10.2 SDRAM Write Accesses ................................................................................................ 9-18
9.10.3 SDRAM Refresh Timing ................................................................................................ 9-20
10.3.1 DMA Mode Register (DMR) ......................................................................................... 10-2
10.3.2 DMA Interrupt Register (DIR) ....................................................................................... 10-4
10.3.3 DMA Source Address Register (DSAR) ........................................................................ 10-5
10.3.4 DMA Destination Address Register (DDAR) ................................................................ 10-6
10.3.5 DMA Byte Count Register (DBCR) ............................................................................... 10-6
11.1.1 Features ........................................................................................................................... 11-1
11.4.1 FEC Frame Reception .................................................................................................... 11-5
11.4.2 CAM Interface ................................................................................................................ 11-6
11.4.3 Ethernet Address Recognition ........................................................................................ 11-6
11.4.4 Hash Table Algorithm ..................................................................................................... 11-8
MCF5272 ColdFire
Table of Contents (Continued)
®
SDRAM Controller
Integrated Microprocessor User’s Manual, Rev. 3
Ethernet Module
DMA Controller
Chapter 10
Chapter 11
Chapter 9
Title
Freescale Semiconductor
Number
Page
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