pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 80

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

4.1.15.3 S
The FALC
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4.1.15.4 Channel Associated Signaling CAS (E1, serial mode)
The signaling information is carried in time slot 16 (TS16). The signaling controller
samples the bit stream either on the receive line side or if external signaling is enabled
on the receive system side. External signaling is enabled by selecting the RSIG pin
function in registers PC(4:1) and setting XSP.CASEN = 1.
Optionally the complete CAS multiframe can be transmitted on pin RSIG. The signaling
data is clocked with the working clock of the receive highway (SCLKR) together with the
receive synchronization pulse (SYPR). Data on RSIG is transmitted in the last 4 bits per
time slot and is aligned to the data on RDO. The first 4 bits per time slot can be optionally
fixed high or low (SIC2.SSF), except for time slot 0 and 16 (bit 1 to 4 are always "0000"
in TS16). In time slot 0 the FAS/NFAS word is transmitted, in time slot 16 the CAS
multiframe pattern "0000XYXX". Data on RSIG is only valid if the freeze signaling status
is inactive. With FMR1.SAIS an all-ones data stream can be transmitted on RDO and
RSIG.
The signaling procedure is done as it is described in ITU-T G.704 and G.732.
The main functions are:
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Updating of the received signaling information is controlled by the freeze signaling
status. The freeze signaling status is automatically activated if a loss-of-signal
(FRS0.LOS = 1), or a loss of CAS multiframe alignment (FRS1.TSL16LFA = 1) or a
receive slip occurs. The current freeze status is output on port FREEZE (RP(A:D)) and
indicated by register SIS.SFS. Optionally automatic freeze signaling can be disabled by
setting bit SIC3.DAF.
After CAS resynchronization an interrupt is generated. Because at this time the signaling
is still frozen, CAS data is not valid yet. Readout of CAS data has to be delayed until the
next CAS multiframe is received.
User’s Manual
Hardware Description
The access through register RSW
The access through registers RSA(8:4), capable of storing the information for a
complete multiframe
The access through the 64 byte deep receive FIFO of the signaling controller of
HDLC channel 1. This S
stream as well as HDLC frames where the signaling controller automatically
processes the HDLC protocol. Any combination of S
and stored in the RFIFO is selected by XC0.SA(8:4). The access to the RFIFO is
supported by ISR0.RME/RPF.
Synchronization to a CAS multiframe
Detection of AIS and remote alarm in CAS multiframes
Separation of CAS service bits X1 to X3
®
56 supports the S
a
-Bit Access (E1)
a
-bit access gives the opportunity to receive a transparent bit
a
-bit signaling of time slot 0 of every other frame as follows:
80
a
-bits which shall be extracted
Functional Description E1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56