pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 214

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

8.1.6
The frames can be transmitted as shown below.
Figure 81
Transmitting an HDLC frame via register CMDR.XTF (or CMDR2.XTF2/CMDR3.XTF3
for channel 2/3), the address, the control fields and the data field have to be entered in
the XFIFO (XFIFO2, XFIFO3).
If CCR2.XCRC (or CCR3.XCRC2/CCR4.XCRC3 for channel 2/3) is set, the CRC
checksum will not be generated internally. The checksum has to be provided via the
transmit FIFO (XFIFO, XFIFO2, XFIFO3) as the last two bytes. The transmitted frame is
closed automatically with a closing flag only.
The FALC
to be transmitted makes sense or not.
8.2
Characteristics: fully transparent
In no HDLC mode, fully transparent data transmission/reception without HDLC framing
is performed, i.e. without flag generation/recognition, CRC generation/check, or bit
stuffing. This feature can be profitably used e.g. for:
•
•
•
Data transmission is always performed out of the XFIFO (XFIFO2, XFIFO3). In
transparent mode, the receive data is shifted into the RFIFO (RFIFO2, RFIFO3).
Note: If a 1-byte frame is sent in extended transparent mode, in addition to interrupt
User’s Manual
Hardware Description
Specific protocol variations
Transmission of a BOM frame (channel 1 only)
Test purposes
Transmit
HDLC
Frame
(XHF)
ISR1.XPR (transmit pool ready) the interrupt ISR1.XDU (transmit buffer underrun)
is set and XFIFO is blocked.
®
Transmit Data Flow
Extended Transparent Mode
56 does not check whether the length of the frame, i.e. the number of bytes
HDLC Transmit Data Flow
FLAG
ADDRESS
ADDR
XFIFO
CONTROL
CTRL
214
Signaling Controller Operating Modes
Ι
DATA
CHECKRAM
CRC
DS1.1, 2003-10-23
PEF 2256 H/E
ITD06456
FALC
FLAG
®
56