pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 106

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

®
FALC
56
PEF 2256 H/E
Functional Description E1
PC(4:1).RPC(2:0) = 001. The RFM selection disables the internal time slot assigner, no
offset programming is performed. The receive frame marker is active high for one
2.048 MHz cycle or one system clock cycle (see GPC1.SRFM) and is clocked off with
the rising or falling edge of the clock which is in/output on port SCLKR (see
SIC3.RESR/X).
Compared to the receive path the inverse functions are performed for the transmit
direction.
The interface to the transmit system highway is realized by two data buses, one for the
data XDI and one for the signaling data XSIG. The time slot assignment is equivalent to
the receive direction.
Latching of data is controlled by the system clock (SCLKX) and the synchronization
pulse (SYPX/XMFS) in combination with the programmed offset values for the transmit
time slot/clock slot counters XC1/0. The frequency of the working clock of
2.048/4.096/8.192/16.384 MHz for the transmit system interface is programmable by
SIC1.SSC1/0. Refer also
toTable
24.
The received bit stream on ports XDI and XSIG can be multiplexed internally on a time
slot basis, if enabled by SIC3.TTRF = 1. The data received on port XSIG can be sampled
if the transmit signaling marker XSIGM is active high. Data on port XDI is sampled if
XSIGM is low for the corresponding time slot. Programming the XSIGM marker is done
with registers TTR(4:1).
User’s Manual
106
DS1.1, 2003-10-23
Hardware Description