pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 175

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

5.5.1.1
Depending on the selection of the synchronization signals (SYPR or RFM), different
calculation formulas are used to define the position of the synchronization pulses. These
formulas are given below, see
of SYPR and RFM is always the basic T1/J1 bit width (648 ns) in 1.544-MHz mode or
the E1 bit width (488 ns) in 2.048-MHz mode.
This chapter describes the system highway operation in 1.544-MHz mode only. If the
system highway is operated in 2.048-MHz mode, the description given in
Chapter 4.5.1.1
SYPR Offset Calculation
T:
SD:
SC:
X:
0 ≤T ≤4:
5 ≤T ≤T
RFM Offset Calculation
MP:
SD:
SC:
X:
0
193 × (SC/SD) - 2 ≤ MP ≤193 × (SC/SD) - 1: X = MP + 2 - (186 × SC/SD)
User’s Manual
Hardware Description
max
Time between beginning of SYPR pulse and beginning of next frame
(time slot 0, bit 0), measured in number of SCLKR clock intervals
maximum delay: T
Basic data rate; 1.544 Mbit/s
System clock rate; 1.544, 3.088, 6.176, or 12.352 MHz
Programming value to be written to registers RC0 and RC1 (see
Marker position of RFM, counting in SCLKR clock cycles (0 = F-bit)
SC = 1.544 MHz:
SC = 3.088 MHz:
SC = 6.176 MHz:
SC = 12.352 MHz: 0 ≤MP ≤1543
Basic data rate; 1.544 Mbit/s
System clock rate; 1.544, 3.088, 6.176, or 12.352 MHz
Programming value to be written to registers RC0 and RC1 (see
:
Receive Offset Programming
X = 4 - T + (7 × SC/SD)
X = (200 × SC/SD) + 4 - T
on
≤ MP ≤193 × (SC/SD) - 3: X = MP + 2 + (7 × SC/SD)
Page 109
max
0 ≤MP ≤192
0 ≤MP ≤385
0 ≤MP ≤771
applies.
Figure 60
= (193 × SC/SD) - 1
to
175
Figure 63
for explanation. The pulse length
Functional Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
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FALC
375).
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