pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 291

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

HDLCI3
Global Clock Mode Register 1 (Read/Write)
Value after reset: 00
GCM1
See
Global Clock Mode Register 2 (Read/Write)
Value after reset: 00
GCM2
See
Global Clock Mode Register 3 (Read/Write)
Value after reset: 00
GCM3
See
Global Clock Mode Register 4 (Read/Write)
Value after reset: 00
GCM4
See
User’s Manual
Hardware Description
Table 64
Table 64
Table 64
Table 64
7
7
7
7
for programming.
for programming.
for programming.
for programming.
Inverse HDLC Operation - HDLC Channel 3
Setting this bit selects the HDLC channel 3 operation mode.
0 =
1 =
H
H
H
H
Normal operation, HDLC attached to line side
Inverse operation, HDLC attached to system side.
HDLC data is received on XDI and transmitted on RDO.
GCM1(7:0)
GCM3(7:0)
GCM4(7:0)
GCM2(7:0
291
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
0
0
0
0
FALC
(93)
(94)
(95)
(92)
®
56