pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 274

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Errored Second Mask (Read/Write)
Value after reset: FF
ESM
ESM
Clock Mode Register 3 (Read/Write)
Value after reset: 00
CMR3
Table 62
CFAX(3:0)
7
4
Disable Error Counter (Write)
Value after reset: 00
DEC
DRBD
DCEC3
DCEC2
DCEC1
User’s Manual
Hardware Description
H
H
DRBD
LFA
7
7
7
DCO-R and DCO-X Corner Frequency Programing (E1)
Errored Second Mask
This register functions as an additional mask register for the interrupt
status bit Errored Second (ISR3.ES). A "1" in a bit position of ESM
deactivates the related second interrupt.
Disable Receive Buffer Delay
This bit has to be set before reading the register RBD. It is reset
automatically if RBD has been read.
Disable CRC Error Counter 3
Disable CRC Error Counter 2
Disable CRC Error Counter
FER
H
CFAX(3:0)
DCO-X Corner
Frequency [Hz]
0.2
2.0
DCEC3 DCEC2 DCEC1
CER
AIS
274
CFAR(3:0)
7
4
LOS
DEBC
CVE
CFAR(3:0)
DCVC
SLIP
DCO-R Corner
Frequency [Hz]
0.2
2.0
DS1.1, 2003-10-23
PEF 2256 H/E
DFEC
EBE
E1 Registers
0
0
0
FALC
(47)
(48)
(60)
®
56