pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 143

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

After reset, the FALC
T1/J1 (PCM24) mode. Switching between the framing formats is done by bit
FMR4.FM1⁄ 0 for the receiver and for the transmitter.
5.2.2
Synchronization status is reported by bit FRS0.LFA (Loss Of Frame Alignment). Framing
errors (pulse frame and multiframe) are counted by the Framing Error Counter FEC.
Asynchronous state is reached if
2 out of 4 (bit FMR4.SSC1/0 = 00), or
2 out of 5 (bit FMR4.SSC1/0 = 01), or
2 out of 6 (bit FMR4.SSC1/0 = 10), or
4 consecutive multiframe pattern in ESF format are incorrect (bit FMR4.SSC1/0 = 11).
If auto mode is enabled, counting of framing errors is interrupted.
The resynchronization procedure is controlled by either one of the following procedures:
•
•
5.2.3
FT and FS bit conditions, i.e. pulse frame alignment and multiframe alignment can be
handled separately if programmed by bit FMR2.SSP. Thus, a multiframe
resynchronization can be automatically initiated after detecting 2 errors out of 4/5/6
consecutive multiframing bits without influencing the state of the terminal framing.
In the synchronous state, the setting of FMR0.FRS or FMR0.EXLS resets the
synchronizer and initiates a new frame search. The synchronous state is reached if there
is only one definite framing candidate. In the case of repeated apparent simulated
candidates, the synchronizer remains in the asynchronous state.
In asynchronous state, the function of FMR0.EXLS is the same as above. Setting bit
FMR0.FRS induces the synchronizer to lock onto the next available framing candidate if
there is one. Otherwise a new frame search is started. This is useful in case the framing
pattern that defines the pulseframe position is imitated periodically by a pattern in one of
the speech/data channels.
The control bit FMR0.EXLS should be used first because it starts the synchronizer to
search for a definite framing candidate.
To observe actions of the synchronizer, the Frame Search Restart Flag FRS0.FSRF is
implemented. It toggles at the start of a new frame search if no candidate has been found
at previous attempt.
User’s Manual
Hardware Description
Automatically (FMR4.AUTO = 1). Additionally, it can be triggered by the user by
setting/resetting one of the bits FMR0.FRS (force resynchronization) or FMR0.EXLS
(external loss of frame).
User controlled, exclusively, by the control bits described above in the non-auto
mode (FMR4.AUTO = 0).
General Aspects of Synchronization
Addition for F12 and F72 Format
®
56 must be programmed with FMR1.PMOD = 1 to enable the
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Functional Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56