pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 326

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

RDO
ALLS
XDU
XMB
SUEX
User’s Manual
Hardware Description
Receive Data Overflow - HDLC Channel 1
This interrupt status indicates that the CPU did not respond fast
enough to an RPF or RME interrupt and that data in RFIFO has been
lost. Even when this interrupt status is generated, the frame continues
to be received when space in the RFIFO is available again.
Note: Whereas the bit RSIS.RDO in the frame status byte indicates
All Sent - HDLC Channel 1
This bit is set if the last bit of the current frame has been sent
completely and XFIFO is empty. This bit is valid in HDLC mode only.
Transmit Data Underrun - HDLC Channel 1
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO and no XME was
issued.
Note: Transmitter and XFIFO are reset and deactivated if this
Transmit Multiframe Begin
This bit is set every 2 ms with the beginning of a transmitted
multiframe related to the internal transmit line interface timing.
Just before setting this bit registers XS(16:1) are copied in the
transmit shift registers. The registers XS(16:1) are empty and has to
be updated otherwise the contents is retransmitted.
Signaling Unit Error Threshold Exceeded - HDLC Channel 1
Masks the indication by interrupt that the selected error threshold for
SS7 signaling units has been exceeded.
0 =
1 =
Note: SUEX is only valid, if SS7 mode is selected.
If SUEX is caused by an aborted/invalid frame, the interrupt will be
issued regularly until a valid frame is received (e.g. a FISU).
Signaling unit error count below selected threshold
Signaling unit error count exceeded selected threshold
whether an overflow occurred when receiving the frame
currently accessed in the RFIFO, the ISR1.RDO interrupt
status is generated as soon as an overflow occurs and does
not necessarily pertain to the frame currently accessed by the
processor.
condition occurs. They are reactivated not before this interrupt
status register has been read. Thus, XDU should not be
masked by register IMR1.
326
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
FALC
®
56