pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 270

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

DXSS
Clock Mode Register 2 (Read/Write)
Value after reset: 00
CMR2
ECFAX
ECFAR
DCOXC
User’s Manual
Hardware Description
ECFAX
7
ECFAR DCOXC
DCO-X Synchronization Clock Source
0 =
1 =
Enable Corner Frequency Adjustment for DCO-X
0 =
1 =
Note:DCO-X must be enabled.
Enable Corner Frequency Adjustment for DCO-R
0 =
1 =
Note:DCO-R must be enabled.
DCO-X Center-Frequency Enable
0 =
1 =
The DCO-X circuitry synchronizes to the internal reference
clock which is sourced by SCLKX/R or RCLK. Since there are
many reference clock opportunities the following internal
prioritizing in descending order from left to right is realized:
LIM1.RL > CMR1.DXSS > LIM2.ELT > current working clock of
transmit system interface.
If one of these bits is set the corresponding reference clock is
taken.
DCO-X synchronizes to an external reference clock provided
on pin XP(A to D) pin function TCLK, if no remote loop is active.
TCLK is selected by PC(4:1).XPC(3:0) = 0011
Corner frequency adjustment is disabled.
Corner
programmed in CMR3.CFAX (see page 274).
Corner frequency adjustment is disabled.
Corner
programmed in CMR3.CFAR (see page 274). LIM2.SCF is
ignored.
The center function of the DCO-X circuitry is disabled.
The center function of the DCO-X circuitry is enabled.
DCO-X centers to 2.048 MHz related to the master clock
reference (MCLK), if reference clock (e.g. SCLKX) is missing.
frequency
frequency
DCF
270
IRSP
adjustment
adjustment
IRSC
is
is
IXSP
enabled,
enabled,
DS1.1, 2003-10-23
B
PEF 2256 H/E
.
IXSC
E1 Registers
0
values
values
FALC
(45)
®
are
are
56