pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 168

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

SS7 support must be activated by setting the MODE register. Data stored in the transmit
FIFO (XFIFO) is sent automatically. The SS7 protocol is supported by the following
hardware features in transmit direction:
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•
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5.4.7.3
The signaling controller inserts the bit stream either on the transmit line side or if external
signaling is enabled on the transmit system side. Signaling data is sourced on port XSIG,
which is selected by register PC(4:1) and FMR5.EIBR = 1.
In external signaling mode the signaling data is sampled with the working clock of the
transmit system interface (SCLKX) together with the transmit synchronous pulse
(SYPX). Data on XSIG is latched in the bit positions 5 to 8 per time slot, bits 1 to 4 are
ignored. The FS/DL-bit is sampled on port XSIG and inserted in the outgoing data
stream. The received CAS multiframe is inserted frame aligned into the data stream on
XDI. Data sourced by the internal signaling controller overwrites the external signaling
data which must be valid during the last frame of a multiframe.
Internal multiplexing of data and signaling data can be disabled on a per time slot basis
(clear channel capability). This is also valid when using the internal and external
signaling mode.
User’s Manual
Hardware Description
Transmission of flags at the beginning of each Signaling Unit
Bit stuffing (zero insertion)
Calculation of the CRC16 checksum:
The transmitter adds the checksum to each Signaling Unit.
Each signaling unit written to the transmit FIFO (XFIFO, 2× 32 bytes) is sent once or
repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has
been transmitted completely, the FALC
containing the forward sequence number (FSN) and the backward sequence number
(BSN) of the previously transmitted signaling unit. Setting bit CCR5.AFX causes Fill
In Signaling Units (FISUs) to be sent continuously, if no HDLC or Signaling Unit (SU)
is to be transmitted from XFIFO. During update of XFIFO, automatic transmission is
interrupted and resumed after update is completed. The internally generated FISUs
contain FSN and BSN of the last transmitted signaling unit written to XFIFO.
Using CMDR.XREP = 1, the contents of XFIFO can be sent continuously. Clearing
of CMDR.XRES/SRES stops the automatic repetition of transmission. This function
is also available for HDLC frames, so no flag generation, CRC byte generation and
bit stuffing is necessary.
Example: After an MSU has been sent repetitively and XREP has been cleared,
FISUs are sent automatically.
CAS Bit-Robbing (T1/J1, serial mode)
168
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56 optionally starts sending of FISUs
Functional Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
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