pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 367

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

LOOP (Read/Write)
Value after reset: 00
LOOP
RTM
ECLB
CLA(4:0)
User’s Manual
Hardware Description
7
Receive Transparent Mode
Setting this bit disconnects control of the internal elastic store from the
receiver. The elastic store is now in a “free running” mode without any
possibility to actualize the time slot assignment to a new frame
position in case of resynchronization of the receiver. This function can
be used together with the “disable AIS to system interface” feature
(FMR2.DAIS) to realize undisturbed transparent reception.
This bit should be enabled in case of unframed data reception mode.
Enable Channel Loop-Back
0 =
1 =
Note:CAS-BR must be switched off (FMR5.EIBR = 0) while channel
Channel Address For Loop-Back
CLA = 1 to 24 selects the channel.
During loop-back, the contents of the associated outgoing channel on
ports XL1/XDOP/XOID and XL2/XDON is equal to the idle channel
code programmed in register IDLE.
RTM
H
Disables the channel loop-back.
Enables the channel loop-back selected by this register.
loop back is enabled.
ECLB
CLA4
367
CLA3
CLA2
CLA1
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
CLA0
0
FALC
(1F)
®
56