pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 218

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

8.3.5
2× 32 byte FIFO buffers are also provided in receive direction for each HDLC channel.
There are different interrupt indications concerned with the reception of data:
•
•
The following figure gives an example of a reception sequence, assuming that a “long”
frame (66 bytes) followed by two short frames (6 bytes each) are received.
Figure 84
8.3.6
The FALC
•
•
•
User’s Manual
Hardware Description
FALC
System
Interface
CPU
Interface
RPF (RPF2, RPF3, receive pool full) interrupt, indicating that a 32-byte block of data
can be read from RFIFO (RFIFO2, RFIFO3) and the received message is not yet
complete.
RME (RME2, RME3, receive message end) interrupt, indicating that the reception of
one message is completed.
Access via registers RSW/XSW
Access via registers RSA(8:4)/XSA(8:4)
capable of storing the information for a complete multiframe
Access via the 64 byte deep receive/transmit FIFO of the integrated signaling
controller (HDLC channel 1 only). This S
receive a transparent bit stream as well as HDLC frames where the signaling
controller automatically processes the HDLC protocol. Enabling is done by setting of
bit CCR1.EITS and resetting of registers TTR(4:1), RTR(4:1) and FMR1.ENSA.
Data written to the XFIFO will be transmitted subsequently in the S
R
®
Receive Frame 1 (66 bytes)
32
HDLC Data Reception
S
56 supports the S
RPF
a
-bit Access (E1)
Interrupt Driven Reception Sequence Example
RD RFIFO
32 bytes
32
RMC
RPF
2
a
-bit signaling of time slot 0 of every other frame as follows:
RF2 RF3
6
RD RFIFO
32 bytes
6
RMC
218
a
RME
-bit access gives the opportunity to transmit/
Signaling Controller Operating Modes
RMC
RME
RMC
RME
DS1.1, 2003-10-23
PEF 2256 H/E
a
-bit positions
FALC
ITD10972
RMC
®
56