pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 169

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

5.4.7.4
The signaling controller inserts the bit stream either on the transmit line side or if external
signaling is enabled on the transmit system side. Signaling data is sourced internally
from registers XS(12:1).
Internal multiplexing of data and signaling data can be disabled on a per time slot basis
(clear channel capability). This is also valid when using the internal and external
signaling mode.
5.4.7.5
The DL-channel protocol is supported as follows:
•
•
The signaling information stored in the XFIFO is inserted in the DL-bits of frame 26 to 72
in F72 format or in every other frame in ESF format. Transmission can be done on a
multiframe boundary (CCR1.XMFA = 1). Operating in HDLC or BOM mode “flags” or
“idle” are transmitted as interframe timefill.
5.4.7.6
According to ANSI T1.403 the FALC
Performance Report (PPR) and transmit it every second in the data link channel of the
extended superframe format (ESF/F24 only). Automatic sending of this report can be
enabled/disabled by the use of bit CCR5.EPR. A single report can be initiated manually
at any time (by setting CMDR2.XPPR = 1).
Performance information is sampled every second and the report contains data of the
last four seconds as shown in the following tables.
User’s Manual
Hardware Description
Access is done on a multiframe basis through registers XDL(3:1) or
HDLC access or transparent transmission (non HDLC mode) from XFIFO (HDLC
channel 1 only)
CAS Bit-Robbing (T1/J1, µP access mode)
Data Link Access in ESF/F24 and F72 Format (T1/J1)
Periodical Performance Report in ESF Format (T1/J1)
®
56 can automatically generate the Periodical
169
Functional Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56