pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 236

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pef2256e

Manufacturer Part Number
pef2256e
Description
E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet

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Transmit Time Slot Register 1 to 4 (Read/Write)
Value after reset: 00
TTR1
TTR2
TTR3
TTR4
TS(31:0)
User’s Manual
Hardware Description
TS16
TS24
TS0
TS8
7
Time Slot
These bits define the transmit time slots on the system highway to be
inserted. Additionally these registers control the XSIGM marker which
can be forced high during the corresponding time slots independently
of bit CCR1.EITS.
A one in the TTR(4:1) bits inserts the corresponding time slot sourced
by the XFIFO in the data received on pin XDI, if bit CCR1.EITS is set.
If SIC3.TTRF is set and CCR1.EITS is cleared insertion of data
received on port XSIG is controlled by this registers.
Assignments:
TS0 → Time slot 0
...
TS31 → Time slot 31
0 =
1 =
TS17
TS25
TS1
TS9
H
, 00
The selected time slot is not inserted into the outgoing data
stream.
The contents of the selected time slot is inserted into the
outgoing data stream from XFIFO. This function is active only if
bit CCR1.EITS is set.
The corresponding time slot is forced high on marker pin
XSIGM.
H
, 00
TS10
TS18
TS26
TS2
H
, 00
H
TS11
TS19
TS27
TS3
236
TS12
TS20
TS28
TS4
TS13
TS21
TS29
TS5
TS14
TS22
TS30
TS6
DS1.1, 2003-10-23
PEF 2256 H/E
TS15
TS23
TS31
TS7
E1 Registers
0
FALC
(10)
(11)
(12)
(13)
®
56

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