pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 378

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

XLT
DAXLT
Idle Channel Code Register (Read/Write)
Value after reset: 00
IDLE
IDL(7:0)
Transmit DL-Bit Register 1-3 (Read/Write)
Value after reset: 00
XDL1
XDL2
XDL3
User’s Manual
Hardware Description
XDL17
XDL27
XDL37
IDL7
7
7
Transmit Line Tristate
0 =
1 =
Disable Automatic Tristating of XL1/2
0 =
1 =
Idle Channel Code
If channel loop-back is enabled by programming the register
LOOP.ECLB = 1, the contents of the assigned outgoing channel on
ports XL1/XL2 or XDOP/XDON is set equal to the idle channel code
selected by this register.
Additionally, the specified pattern overwrites the contents of all
channels of the outgoing PCM frame selected by the idle channel
registers ICB(3:1). IDL7 is transmitted first.
XDL16
XDL26
XDL36
H
H
, 00
Normal operation
Transmit line XL1/XL2 or XDOP/XDON are switched into
high-impedance state. If this bit is set the transmit line monitor
status information is frozen (default value after hardware reset).
Normal operation. If a short is detected on pins XL1/2 the
transmit line monitor sets the XL1/2 outputs into a
high-impedance state.
If a short is detected on pins XL1/2, the automatic setting of
these pins into a high-impedance state (by the XL-monitor) is
disabled.
H
, 00
XDL15
XDL25
XDL35
H
XDL14
XDL24
XDL34
378
XDL13
XDL23
XDL33
XDL12
XDL22
XDL32
XDL11
XDL21
XDL31
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
XDL10
XDL20
XDL30
IDL0
0
0
FALC
(2B)
(2C)
(2D)
(2E)
®
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