pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 383

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Line Interface Mode 1 (Read/Write)
Value after reset: 00
LIM1
CLOS
RIL(2:0)
DCOC
User’s Manual
Hardware Description
CLOS
7
Clear data in case of LOS
0 =
1 =
Receive Input Threshold
Only valid if analog line interface is selected (LIM1.DRS = 0).
“No signal” is declared if the voltage between pins RL1 and RL2 drops
below the limits programmed by bits RIL(2:0) and the received data
stream has no transition for a period defined in the PCD register.
The threshold where “no signal” is declared is programmable by the
RIL(2:0) bits.
See the DC characteristics for detail.
DCO-R Control
0 =
1 =
Note:If IPC.SSYF = 1, external reference clock frequency is 8.0 kHz
RIL2
H
independent of DCOC.
normally in long-haul mode
In long-haul mode received data is cleared (driven low), as
soon as LOS is detected
Normal receiver mode, receive data stream is transferred
1.544 MHz reference clock for the DCO-R circuitry provided on
pin SYNC.
2.048 MHz reference clock for the DCO-R circuitry provided on
pin SYNC.
RIL1
RIL0
383
DCOC
JATT
RL
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
DRS
0
FALC
(37)
®
56