pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 240

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Framer Mode Register 1 (Read/Write)
Value after reset: 00
FMR1
MFCS
AFR
ENSA
User’s Manual
Hardware Description
MFCS
7
Multiframe Force Resynchronization
Only
(FMR2.RFS(1:0) = 10).
A transition from low to high initiates the resynchronization procedure
for CRC-multiframe alignment without influencing doubleframe
synchronous state. In case, “Automatic Force Resynchronization”
(FMR1.AFR) is enabled and multiframe alignment cannot be
regained, a new search of doubleframe (and CRC multiframe) is
automatically initiated.
Automatic Force Resynchronization
Only
(FMR2.RFS(1:0) = 10).
If this bit is set, a search of doubleframe alignment is automatically
initiated if two multiframe patterns with a distance of n × 2 ms have
not been found within a time interval of 8 ms after doubleframe
alignment has been regained or command FMR1.MFCS has been
issued.
Enable S -Bit Access through Register XSA4-8
Only applicable if FMR1.XFS is set.
0 =
1 =
AFR
H
XSW.XY(4:0) and written to bits RSW.RY(4:0).
S
registers XSA(8:4). In addition, the received information is
written to registers RSA(8:4). Transmitting of the contents of
registers XSA(8:4) is disabled if one of time slot 0 transparent
modes is enabled (XSP.TT0 or TSWM.SA(8:4)).
Normal operation. The S
a
valid
valid
-bit register access. The S
ENSA
if
if
PMOD
CRC
CRC
240
XFS
multiframe
multiframe
a
-bit information is taken from bits
a
-bit information is taken from the
ECM
SSD0
format
format
DS1.1, 2003-10-23
PEF 2256 H/E
XAIS
E1 Registers
is
is
0
FALC
selected
selected
(1D)
®
56