pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 52

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 8
ALE
V
V
switching
The assignment of registers with even/odd addresses to the data lines in case of 16-bit
register access depends on the selected microprocessor interface mode:
Intel
Motorola
Data Lines
n: even address
3.3.1.2
In transmit and receive direction of the signaling controller 64-byte deep FIFOs are
provided for the intermediate storage of data between the system internal highway and
the CPU interface. The FIFOs are divided into two halves of 32 bytes. Only one half is
accessible to the CPU at any time.
In case 16-bit data bus width is selected by fixing pin DBW to logical 1 word access to
the FIFOs is enabled. Data output to bus lines D(15:0) as a function of the selected
interface mode is shown in
allowed. The effective length of the accessible part of RFIFO can be changed from
32 bytes (reset value) down to 2 bytes.
User’s Manual
Hardware Description
SS
SS
/V
/V
DD
DD
FIFO Structure
IM
1
0
0
Selectable Bus and Microprocessor Interface Configuration
D15
Microprocessor interface
Motorola
Intel
Intel
(Address n + 1)
(Address n)
↑
↓
Figure 6
and
D8
52
Figure
7. Of course, byte access is also
D7
Functional Description E1/T1/J1
(Address n)
(Address n + 1)
Bus Structure
de-multiplexed
de-multiplexed
multiplexed
↑
↓
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
D0
®
56