pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 316

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

CRC Error Counter 3 (Read)
CEC3L
CEC3H
CE(15:0)
CE(7:2)
CE(1:0)
User’s Manual
Hardware Description
CE15
CE7
7
7
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then reset automatically. The latched error
counter state should be read within the next second.
CRC Error Counter (detected at T Reference Point in S
GCR.ECMC = 0: If doubleframe format is selected, CEC3H/L has no
function. If CRC-multiframe mode is enabled, CEC3H/L works as
S
sequence 0010 and 0011in every received CRC submultiframe.
Incrementing the counter is only possible in the multiframe
synchronous state FRS0.LMFA = 0.
S
SA61 is received in frame 1 or 9 in every multiframe. The error
counter does not roll over.
During alarm simulation, the counter is incremented once per
submultiframe up to its saturation.
Multiframe Counter
GCR.ECMC = 1: This 6 bit counter increments with each multiframe
period in the asynchronous state FRS0.LFA/LMFA = 1.
During alarm simulation, the counter is incremented once per
multiframe up to its saturation.
Change of Frame Alignment Counter
GCR.ECMC = 1: This 2 bit counter increments with each detected
change of frame/multiframe alignment. The error counter does not roll
over.
During alarm simulation, the counter is incremented once per
multiframe up to its saturation.
Clearing and updating the counter is done according to bit
FMR1.ECM.
a
a
6-bit error indication counter (16 bits) which counts the S
6-bit sequence: SA61, SA62, SA63, SA64 = 0010 or 0011 where
316
DS1.1, 2003-10-23
PEF 2256 H/E
CE0
CE8
E1 Registers
0
0
FALC
a
6 -Bit)
(5A)
(5B)
a
6-bit
®
56