pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 29
pef2256e
Manufacturer Part Number
pef2256e
Description
E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF2256E.pdf
(518 pages)
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Table 1
Pin or
Ball No.
55 (C9)
57 (C7)
User’s Manual
Hardware Description
Name
BHE
BLE
INT
Pin Definitions - Microprocessor Interface (cont’d)
Pin
Type
I
I
O
Buffer
Type
PU
PU
oD/PP Interrupt Request
Function
Bus High Enable
Used in Intel bus mode. If 16-bit bus interface
mode is enabled, this signal indicates a data
transfer on the upper byte of the data bus
D(15:8). In 8-bit bus interface mode this
signal has no function and should be tied to
V
Bus Low Enable
Used in Motorola bus mode. If 16-bit bus
interface mode is enabled, this signal
indicates a data transfer on the lower byte of
the data bus D(7:0). In 8-bit bus interface
mode this signal has no function and should
be tied to
This signal serves as general interrupt
request for all interrupt sources. These
interrupt sources can be masked via registers
IMR(5:0). Interrupt status is reported via
registers GIS (Global Interrupt Status) and
ISR(5:0).
Output characteristics (push-pull active
low/high, open drain) are determined by
programming register IPC.
29
DD
or left open.
V
DD
or left open
External Signals
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56
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