pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 34

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 3
Pin or
Ball No.
73 (C4)
79 (A2)
76 (B4)
User’s Manual
Hardware Description
Name
MCLK
SYNC
CLK1
Pin Definitions - Clock Interface
Pin
Type
I
I
O
Buffer
Type
PU
PU
Function
Master Clock
A reference clock of better than ± 32 ppm
accuracy in the range of 1.02 to 20 MHz must
be provided on this pin. The FALC
internally derives all necessary clocks from
this master (see registers GCM(8:1) for more
detail).
Clock Synchronization of DCO-R
If a clock is detected on pin SYNC the DCO-R
circuitry of the FALC
1.544/2.048 MHz clock (see LIM0.MAS,
CMR1.DCS and CMR2.DCF). Additionally, in
master mode the FALC
synchronize to an 8-kHz reference clock
(IPC.SSYF = 1).
DCO-R Clock Output
Output of the de-jittered system clock
generated by the DCO-R circuit. Frequency
selection is done by setting control bits in
PC5/6. Selectable frequencies are:
E1: 16.384 MHz, 8.192 MHz, 4.096 MHz,
2.048 MHz or 8 kHz
T1/J1: 16.384 MHz, 12.352 MHz, 8.192 MHz,
6.176 MHz, 4.096 MHz, 3.088 MHz,
2.048 MHz, 1.544 MHz or 8 kHz
After reset this output is inactive and
internally pulled high.
Note: If DCO-R is not active
34
(SIC1.RBS(1:0) = 11
CMR1.RS1 = 0
pin CLK1.
®
56 synchronizes to this
B
), no clock is driven on
®
56 is able to
B
External Signals
DS1.1, 2003-10-23
and
PEF 2256 H/E
®
FALC
56
®
56