pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 43

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 4
Pin or
Ball No.
60 (B8)
61 (A9)
62 (A8)
63 (B7)
User’s Manual
Hardware Description
Name
XPA
XPB
XBC
XPD
Pin Definitions - System Interface (cont’d)
Pin
Type
I
I
Buffer
Type
PU
PU
Function
Transmit Multifunction Ports
Depending on programming of bits
PC(1:4).XPC(3:0) these multifunction ports
carry information to the system interface or
from the system to the FALC
the ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is
achieved automatically. Depending on bit
SIC3.RESX latching/transmission of data is
done with the rising or falling edge of SCLKX.
If not connected, an internal pullup transistor
ensures a high input level.
Each input function (SYPX, XMFS, XSIG or
TCLK) may only be selected once. SYPX and
XMFS must not be used in parallel.
Selectable pin functions are described below.
Synchronous Pulse Transmit (SYPX)
PC(1:4).XPC(3:0) = 0000
Together with the values of registers XC(0:1)
this signal defines the beginning of time slot 0
at system highway port XDI . The pulse cycle
is an integer multiple of 125 µs. SYPX must
not be used in parallel with XMFS.
Transmit Multiframe Synchronization
(XMFS)
PC(1:4).XPC(3:0) = 0001
This port defines the frame and multiframe
begin on the transmit system interface ports
XDI and XSIG. Depending on PC5.CXMFS
the signal on XMFS is active high or low.
XMFS must not be used in parallel with
SYPX.
Note: A new multiframe position has settled
43
at least one multiframe after pulse
XMFS has been supplied.
B
B
External Signals
DS1.1, 2003-10-23
®
PEF 2256 H/E
56. After reset
FALC
®
56