pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 398

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

IXSP
IXSC
User’s Manual
Hardware Description
Internal Transmit System Frame Sync Pulse
0 =
1 =
Internal Transmit System Clock
0 =
1 =
The frame sync pulse for the transmit system interface is
internally sourced by the DCO-R circuitry. Additionally, the
external XMFS signal defines the transmit multiframe begin.
The working clock for the transmit system interface is sourced
by SCLKX.
The working clock for the transmit system interface is sourced
internally by the working clock of the receive system interface.
SCLKX is ignored.
The frame sync pulse for the transmit system interface is
sourced by SYPX.
XMFS is enabled or disabled by the multifunction port
configuration. For correct operation bits CMR2.IXSC/IRSC
must be set. SYPX is ignored.
398
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56