pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 228

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

XREP
XRES
XHF
XTF
XME
SRES
User’s Manual
Hardware Description
The receive line interface except the clock and data recovery unit
(DPLL), the receive framer, the one-second timer and the receive
signaling controller are reset. However the contents of the control
registers is not deleted.
Transmission Repeat - HDLC Channel 1
If XREP is set together with XTF (write 24
repeatedly transmits the contents of the XFIFO (1 to 32 bytes) without
HDLC framing fully transparently, i.e. without flag, CRC.
The cyclic transmission is stopped with a SRES command or by
resetting XREP.
Transmitter Reset
The transmit framer and transmit line interface excluding the system
clock generator and the pulse shaper are reset. However the contents
of the control registers is not deleted.
Transmit HDLC Frame - HDLC Channel 1
After having written up to 32 bytes to the XFIFO, this command
initiates the transmission of a HDLC frame.
Transmit Transparent Frame - HDLC Channel 1
Initiates the transmission of a transparent frame without HDLC
framing.
Transmit Message End - HDLC Channel 1
Indicates that the data block written last to the transmit FIFO
completes the current frame. The FALC
transmission operation properly by appending the CRC and the
closing flag sequence to the data.
Signaling Transmitter Reset - HDLC Channel 1
The transmitter of the signaling controller is reset. XFIFO is cleared of
any data and an abort sequence (seven 1's) followed by interframe
time fill is transmitted. In response to SRES a XPR interrupt is
generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Note: The maximum time between writing to the CMDR register and
Note:During cyclic transmission the XREP-bit has to be set with
every write operation to CMDR.
the execution of the command takes 2.5 periods of the current
system data rate. Therefore, if the CPU operates with a very
228
H
to CMDR), the FALC
®
56 can terminate the
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
FALC
®
®
56
56