pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 171

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 44
Bit Value
G1 = 1
G2 = 1
G3 = 1
G4 = 1
G5 = 1
G6 = 1
SE = 1
FE = 1
LV = 1
SL = 1
LB = 1
U1
U2
R
NmNi
1)
5.5
The FALC
receive direction different system clocks and system pulses are necessary. The interface
to the receive system highway is realized by two data buses, one for the data RDO and
one for the signaling data RSIG. The receive highway is clocked on pin SCLKR, while
the interface to the transmit system highway is independently clocked on pin SCLKX.
The
2.048/4.096/8.192/16.384/1.544/3.088/6.192/12.352 Mbit/s for the receive and transmit
system interface is programmable by SIC1.SSC1/0, SIC2.SSC2 and SIC1.SSD1,
FMR1.SSD0. Selectable system clock and data rates and their valid combinations are
shown in the table below.
User’s Manual
Hardware Description
according to ANSI T1.403
frequency
®
System Interface in T1/J1 Mode
56 offers a flexible feature for system designers where for transmit and
Bit Functions in Periodical Performance Report
Interpretation
Number of CRC error events = 1
1 < number of CRC error events ≤ 5
5 < number of CRC error events ≤ 10
10 < number of CRC error events ≤ 100
100 < number of CRC error events ≤ 319
Number of CRC error events ≥ 320
Severely errored framing event ≥ 1 (FE shall be 0)
Frame synchronization bit error event ≥ 1 (SE shall be 0)
Line code violation event ≥ 1
Slip event ≥ 1
Payload loop-back activated
Not used (default value = 0)
Not used (default value = 0)
Not used (default value = 0)
One-second report modulo 4 counter
of
these
working
171
clocks
and
Functional Description T1/J1
the
1)
data
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
rate
®
56
of