pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 164

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

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The functions of the transmit buffer are:
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Writing of received data from XDI is controlled by SCLKX/R and SYPX/XMFS in
combination with the programmed offset values for the transmit time slot/clock slot
counters. Reading of stored data is controlled by the clock generated by DCO-X circuitry
or the externally generated TCLK and the transmit framer. With the de-jittered clock data
is read from the transmit elastic buffer and are forwarded to the transmitter. Reporting
and controlling of slips is automatically done according to the receive direction.
Positive/negative slips are reported in interrupt status bits ISR4.XSP and ISR4.XSN.
A reinitialization of the transmit memory is done by reprogramming the transmit time slot
counter XC1 and with the next SYPX pulse. After that, this memory has its optimal start
position.
The frequency of the working clock for the transmit system interface is programmable by
SIC1.SSC1/0 and SIC2.SSC2 in a range of 1.544 to 12.352 MHz/2.048 to 16.384 MHz.
Generally the data or marker on the system interface are clocked off or latched on the
rising or falling edge (SIC3.RESX) of the SCLKX clock. Some clocking rates allow
transmission of time slots/marker in different channel phases. Each channel phase
User’s Manual
Hardware Description
Maximum of wander: 70 UI in channel translation mode 0
Maximum of wander: 45 UI in channel translation mode 1
System interface clocking rate: modulo 1.544 MHz:
Maximum of wander: 74 UI
average delay after performing a slip: 96 bits
XBS1/0 = 10: two frame buffer or 386 bits
System interface clocking rate: modulo 2.048 MHz:
142 UI in channel translation mode 0
78 UI in channel translation mode 1
System interface clocking rate: modulo 1.544 MHz:
Maximum of wander: 140 UI
average delay after performing a slip: 193 bits
XBS1/0 = 11: short buffer or 96 bits:
System interface clocking rate: modulo 2.048 MHz:
Maximum of wander: 28 UI in channel translation mode 0; channel translation mode
1 not supported
System interface clocking rate: modulo 1.544 MHz:
Maximum of wander: 38 UI
average delay after performing a slip: 48 bits
Clock adaption between system clock (SCLKX/R) and internally generated transmit
route clock (XCLK) or externally sourced TCLK.
Compensation of input wander and jitter.
Frame alignment between system frame and transmit route frame
Reporting and controlling of slips
164
Functional Description T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
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