pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 55

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

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FALC
56
PEF 2256 H/E
Functional Description E1/T1/J1
interrupt source register. After reading the assigned interrupt status registers ISR(5:0),
the pointer in register GIS is cleared or updated if another interrupt requires service.
If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes
inactive. Updating of interrupt status registers ISR(5:0) and GIS is only prohibited during
read access.
Masked Interrupts Visible in Status Registers
Each interrupt source can be individually masked to prevent an interrupt to be generated.
Only unmasked interrupts trigger the interrupt line and are visible in their interrupt status
register. The Global Interrupt Status register (GIS) indicates those interrupt status
registers with active interrupt indications (GIS.ISR(5:0)).
An additional mode can be selected via bit GCR.VIS. In this mode, masked interrupt
status bits neither generate an interrupt on pin INT nor are they visible in GIS, but are
displayed in the corresponding interrupt status register(s) ISR(5:0).
This mode is useful when some interrupt status bits are to be polled in the individual
interrupt status registers.
Please note that whenever polling is used, all interrupt status registers concerned have
to be polled individually (no “hierarchical” polling possible), since GIS only contains
information on actually generated, which means unmasked interrupts.
User’s Manual
55
DS1.1, 2003-10-23
Hardware Description