pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 105

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

If the FALC
the FALC
4.5
The FALC
receive direction different system clocks and system pulses are necessary. The interface
to the receive system highway is realized by two data buses, one for the data RDO and
one for the signaling data RSIG. The receive highway is clocked on pin SCLKR, while
the interface to the transmit system highway is independently clocked on pin SCLKX.
The
2.048/4.096/8.192/16.384 Mbit/s for the receive and transmit system interface is
programmable by SIC1.SSC1/0, and SIC1.SSD1, FMR1.SSD0. Selectable system clock
and data rates and their valid combinations are shown in the table below
Table 24
System Data Rate
2.048 Mbit/s
4.096 Mbit/s
8.192 Mbit/s
16.384 Mbit/s
× = valid, - = invalid
Generally the data or marker on the system interface are clocked off or latched on the
rising or falling edge (SIC3.RESR/X) of the SCLKR/X clock. Some clocking rates allow
transmission of time slots in different channel phases. Each channel phase which shall
be active on ports RDO, XDI, RP(A:D) and XP(A:D) is programmable by SIC2.SICS(2:0),
the remaining channel phases are cleared or ignored.
The signals on pin SYPR together with the assigned time slot offset in register RC0 and
RC1 define the beginning of a frame on the receive system highway.The signal on pin
SYPX or XMFS together with the assigned time slot offset in register XC0 and XC1
define the beginning of a frame on the transmit system highway.
Adjusting the frame begin (time slot 0, bit 0) relative to SYPR/X or XMFS is possible in
the range of 0 to 125 µs. The minimum shift of varying the time slot 0 begin can be
programmed between 1 bit and 1/8 bit depending of the system clocking and data rate,
e.g. with a clocking/data rate of 2.048 MHz shifting is done bit by bit, while running the
FALC
A receive frame marker RFM can be activated during any bit position of the entire frame.
Programming is done with registers RC1/0. The pin function RFM is selected by
User’s Manual
Hardware Description
®
56 with 16.384 MHz and 2.048 Mbit/s data rate it is done by 1/8 bit.
frequency
®
56 undisturbedly.
®
System Interface in E1 Mode
®
56 offers a flexible feature for system designers where for transmit and
56 is configured for no signaling, the system interface data stream passes
System Clocking and Data Rates (E1)
of
Clock Rate
2.048 MHz
×
-
-
-
these
working
Clock Rate
4.096 MHz
×
×
-
-
105
clocks
Clock Rate
8.192 MHz
×
×
×
-
and
Functional Description E1
the
data
DS1.1, 2003-10-23
PEF 2256 H/E
Clock Rate
16.384 MHz
×
×
×
×
FALC
rate
®
56
of