pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 337

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Receive Byte Count Register 2 (Read)
Value after reset: 00
RBC2
OV2
RBC2(6:0)
Receive Byte Count Register 3 (Read)
Value after reset: 00
RBC3
OV3
RBC3(6:0)
Signaling Status Register 2 (Read)
Value after reset: 00
SIS2
XDOV2
User’s Manual
Hardware Description
XDOV2
OV2
OV3
Counter Overflow - HDLC Channel 2
0 =
1 =
Receive Byte Count - HDLC Channel 2
Indicates the length of a received frame.
Counter Overflow - HDLC Channel 3
0 =
1 =
Receive Byte Count - HDLC Channel 3
Indicates the length of a received frame.
Transmit Data Overflow - HDLC Channel 2
More than 32 bytes have been written to the XFIFO2.
This bit is reset
RBC26
RBC36
XFW2
•by a transmitter reset command XRES or
•when all bytes in the accessible half of the XFIFO2 have been
H
H
H
moved in the inaccessible half.
Less than or equal to 128 bytes received
More than 128 bytes received
Less than or equal to 128 bytes received
More than 128 bytes received
XREP2
RBC25
RBC35
RBC24
RBC34
337
RBC23
RBC33
RLI2
RBC22
RBC32
CEC2
RBC21
RBC31
DS1.1, 2003-10-23
RBC20
RBC30
PEF 2256 H/E
E1 Registers
FALC
(A9)
(90)
(91)
®
56