PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 98

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

S-bit
The S-bit received on the U
stream, and is logical OR’ ed with the detected far-end code violation. The result is sent
to the DELIC as status bit ’FECV’.
In transmit direction, the S-bit value is sent in the data stream from the DELIC to the VIP,
and passed on transparently to the U
in DELIC’s data RAM. It is required e.g. for switching a digital loop in the terminal.
CV-bit
The code violation bit received on the line is not transmitted to the DELIC.
4.2.7.3
A DC-balancing bit is inserted by the VIP according to the Balancing Bit Control (BBC)
bit transmitted to the VIP on the command line.
In receive direction, the DC balancing bit is received, but not evaluated.
4.2.7.4
The data is received and transmitted at a nominal bit rate of 384 kbit/s. In the first half of
the 4 kHz U
the frame ‘zeros’ are transmitted and data is received.
Scrambling and de-scrambling of the B-channel data is done automatically. The received
and transmitted data is stored in the Data RAM in the following format:
U
In transmit direction, depending on the multiframe position, the M-bit contains either the
T-bit or the S-bit with the following functionality:
• T-bit: a) D-channel available info to the terminal
• S-bit: switches remote loop in terminal device
Data Sheet
PN
Mode Receive / Transmit Data Format
7
D-channel
b) DECT synchronization signal
DC-Balancing Bit
U
PN
PN
frame data is transmitted and ‘zeros’ are received, in the second half of
6
Mode Data Format
Operation Mode Command/Status bits
M-bit
5
PN
line interface is extracted by the VIP out of the data
B1-channel data
B2-channel data
PN
4
x
terminal. The S-bit value may be programmed
81
3
x
2
x
Functional Description
1
x
PEB 20570
PEB 20571
2003-07-31
0
x