PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 103

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

4.2.9.1
Figure 28
Transmit Direction
• Since the DELIC is master in the LT-S mode, all transmitted frames always start with
• The F-, L- and N-bits are generated and inserted into the S/T frame
• The information about D-channel availability is transmitted at the E-bit position
• The B- and D-channel data, A-, F
Receive Direction
• The received frame start is recognized by the F-bit. Since the received frames start at
• The received L-bits are discarded
• The B- and D-channel data bits and F
Data Sheet
the FSC-2000 (the transmission starts from ch-0.bit-0 which is followed by ch_1.bit_0,
ch_2.bit_0,... ch_7.bit_0, ch_0.bit_1, etc.; see also
inserted into transmitted S/T frame by the IOM-2000
different points of time (due to the different line delays) the frame start recognition is
performed for each channel separately
Rx
Tx
Rx:
Tx:
VIP hardware:
F-bit & CV detection
FIFOs: -for jitter etc.
VIP hardware:
F-bit & CV generation
Inversion of data (B1, B2, D)
E-bit mirroring
Inversion of data (B1, B2, D)
VIP
Rx FIFOs
LT-S mode
F
F,L
Handling of So Frame in LT-S Mode (One Channel)
INV
INV
TRANSIU
TRANSIU hardware:
Control of E-bit mirroring
F-bit recognition
L-bit discard
TRANSIU hardware:
F-, L-, N-bit generation
SYNC
a
-, M- and S-bits are prepared by the DSP and
a
-bit are arranged in the Data RAM
Tx buffer
Rx buffer
86
250 µs
M
F
A
Figure
S-FIFO
Q-FIFO
INFO 2,4 recognition
F
DSP software:
DSP software:
S-bit handling (8-bit service ch.)
Control of E-bit mirroring
Generation of complete S frame
Multiframe generation
A
-bit handling (4-bit Q-channel)
12)
Functional Description
DSP
PEB 20570
PEB 20571
DELIC
2003-07-31