PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 287

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

8.6.6
Table 80
Parameter
DR setup time before
DCL_2000 falling edge
DR hold time after
DCL_2000 falling edge
DX delay after DCL_2000
rising edge
STAT setup time before
DCL_2000 falling edge
STAT hold time after
DCL_2000 falling edge
CMD delay after
DCL_2000 rising edge
FSC rising edge delay
after DCL_2000 rising
edge
(In both, long and short
pulse FSC cycles)
FSC falling edge delay
after DCL_2000 rising
edge
FSC falling edge delay
after DCL_2000 falling
edge
FSC Clock Period
1)
2)
Data Sheet
FSC is the same pin used for the IOM-2 interface
it’s designed to be sampled with the falling edge of DCL_2000 at any chip connected to the IOM-2000 interface.
The first DCL-2000 cycle in which FSC is sampled as logic-1 after a sampling of logic-0, is considered as the
first cycle of the new IOM-2000 frame. When a long-pulse FSC cycle is issued, FSC always rises and falls with
a rising edge of DCL_2000, and it is generated with a 50% duty cycle.
FSC Control Register : EFSCD (bit 2) = ‘0’, i.e. no delay between DCL_2000 rising edge and FSC rising edge.
“FSC Control Register” on Page 239
1)
4)
IOM-2000 Interface Timing
IOM-2000 Interface Timing
Symbo
l
t
t
t
t
t
t
t
t
t
t
DSF
DHF
XDR
SSF
SHF
CDR
FRE
FFE
FFF
FCD
Electrical Characteristics and Timing Diagrams
min.
1
12
1
12
-10
6
-10
70
Limit Values
(Table
270
typ.
125
76). FSC rises with a rising edge of DCL_2000, and
max.
26
20
20
10
26
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
CFSC:EFSCD = ‘0’
CFSC:EFSCD = ‘1’
Long-pulse FSC cycle
Short-pulse FSC cycle
DCL_2000 = 3072
kHz
DCL = 4096 kHz
PEB 20570
PEB 20571
2003-07-31
3)
2)