PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 157

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

If the DMA controller grants the bus to the DELIC, it drives DACK low and begins toggling
the control lines.
In Memory-to-Memory mode on Intel / Infineon bus type, it drives RD line low when
reading from the receive mailbox. The WR line stays high during all the “Read” transfer.
DACK functions as a CS and is driven low during each “Read” access.
In Memory-to-Memory mode on Motorola bus type, the DMAC drives R/W line ’high’
during ‘Read’ operations while DACK is low and DS controls the read access. In Fly-by
mode the meaning of ‘Read’ and ‘Write’ commands is opposite for the mailbox
Chapter
by one. DMA-operation finishes with the count down from ´0
The DMA controller can stop the transaction (before frame end) driving DACK high. The
DELIC continues driving DREQR active, stops decrementing DRXCNT and waits until
DACK becomes low again.
After the DMA controller has read the requested number of bytes from the receive
mailbox, DRXCNT becomes ’F
programmed to cause an interrupt (INT0) to the OAK.
Figure 56
Receive Data via the Receive Mailbox-Steps
1. The OAK writes the received data to into the receive mailbox.
2. The OAK writes the number of bytes to be transferred minus one into DRXCNT
3. DREQR is asserted (“high” or “low”).
Data Sheet
(Rc_Num).
DREQR
DSP-tasks
DACK
RD
4.10.1.2). After each ‘Read’ operation the counter (DRXCNT) is decremented
Timing in two-cycle DMA Mode for Receive Direction and Infineon/
Intel Bus Type
WR
DRXCNT
1
H
’, and DREQR is deasserted. DINSTA can be
2
140
16
OAK -
INT0
ISR INT0:
WR DRXCNT
H
´ to the value ’F
Functional Description
PEB 20570
PEB 20571
2003-07-31
H
’.
(see