PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 130

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PEB20571FV31XP

Manufacturer Part Number
PEB20571FV31XP
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB20571FV31XP

Lead Free Status / Rohs Status
Compliant
4.6
4.6.1
High-level data link control (HDLC) is a most common protocol in the data link layer, layer
2 of the OSI model. Signalling protocols LABD and LAPB are based on HDLC and its
framing structure: Opening Flag, Address Field, Control Field, Data Field, CRC, Closing
Flag, Interframe Timefill.
HDLC uses a zero insertion/deletion process (bit-stuffing) to ensure that a data bit
pattern matching the delimiter flag (01111110 = 7EH) does not occur in a field between
the starting and the closing flag. The HDLC frame is synchronous. An address field is
needed to carry the frame's destination address because the frame can be sent to
different systems. An address field can be 8, or 16 bits long, depending on the data link
layer protocol. LAPB uses an 8-bit address, LAPD 16-bit address. The length of the data
in the data field depends on the frame protocol. Error control is implemented by
appending a cyclic redundancy check (CRC) to the frame, which is 16 bits long.
The multichannel HDLC controller within the DELIC consists of two parts: a hardware
block (HDLC Unit) and a dedicated on-chip processor (OAK DSP). The processor
handles the HDLCU by writing/reading signalling data and reacts on slow events by
software.
The following table shows the main HDLC features and the responsible unit for its
handling:
Note: The multichannel HDLC Unit is not connected to any DELIC pin.
Data Sheet
HDLC Features
Flag detection and generation
Zero insertion/deletion (bit stuffing)
16-bit CRC-CCITT generation and checking
Time slot assignment (2- or 16-bit)
Programmable flags between successive frames
Flexible address handling
Flexible buffers management (per frame)
Separate interrupts for frames and buffers (Rx and Tx)
Flag/abort/idle generation and detection
Detection of non-octet aligned frames
Automatic retransmission in case of collision
HDLC Unit
HDLC Overview
113
HDLC Unit
X
X
X
X
X
X
Functional Description
Processor
X
X
X
X
X
X
X
PEB 20570
PEB 20571
2003-07-31

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