PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 83

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

3.4.3
The internal interface between the on-chip DSP and µP is established by two Mailboxes:
a ’general’ Mailbox and a dedicated DMA Mailbox. The non-DMA mode provides the
option to combine them together building a double-sized ’general’ Mailbox. The DELIC
is configured to DMA or non-DMA mode by a dedicated bit in the µP interface
configuration register (MCFG:DMA).
DMA Mode
The DMA Mailbox can be accessed only by a DMA controller. The DACK input pin
(together with the RD and WR signals) is used to access the DMA Mailbox. Only the
general Mailbox can be accessed directly by the µP. In DMA mode, the pin DACK/A4 is
used as DACK, and A4 of the A-bus or AD-bus coming from the µP must not be used as
an address line for the DELIC. In this case A4 is driven internally to ‘0’.
Note: In de-multiplexed mode AD4 should be connected to DELIC’s D4input pin.
Non-DMA mode
This is the default mode (after reset).The general Mailbox and the DMA Mailbox data
registers are concatenated into one double-sized general Mailbox, accessible by the µP.
This broad Mailbox consists of a dedicated µP Mailbox and a DSP Mailbox. Each of them
contains 32 data bytes and 1 command byte. In non-DMA mode, DACK/A4 is used as
A4, in order to include the DMA Mailbox data registers in the µP interface address space.
3.4.4
The DELIC contains only one source for an external interrupt - the general Mailbox. This
interrupt source is the OCMD register of the DSP Mailbox. Releasing the interrupt is
done by the µP resetting bit OBUSY:BUSY. Masking it may be done by resetting the
MASK bit of the µP interface Configuration Register (MCFG:IMASK).
The interrupt vector issued is the contents of the DSP Mailbox command register MCMD.
In Motorola mode, the interrupt vector is issued upon the first IACK pulse, while in
Infineon/Intel mode it is issued upon the second IACK pulse. In the latter case, the
interrupt vector due to the first IACK pulse (if needed), should be issued by an external
interrupt controller.
Data Sheet
DMA or Non-DMA Mode
DELIC External Interrupts
66
Interface Description
PEB 20570
PEB 20571
2003-07-31