PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 135

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

The processor handles the HDLCU (tasks 1) during every IOM frame, i.e. every 125 s.
If a 16-kbit/s channel is handled, the task 2 is performed about every 4th to 5th frame (4
x 2-bit writing to the HDLCU minus “0-detection” => 8-bit output).
At the beginning of a frame, the DSP checks if the HDLCU is busy (HHOLD = ’0’).
The DSP may only access the buffers and command RAM when DSPCTRL = ‘1’.
In transmit direction, the DSP writes data 8-bit wise into the Transmit Input Buffers,
reads the processed data from the Transmit Output Buffers and places the coded data
into the assigned destination time slot like in the following example:
• 2-bit wise writing into the D-channel of an IOM-2 interface of the IOM Unit, or into the
• 8-bit wise writing into a signalling channel of the PCM highway by writing into the PCM
In general, the HDLC controller can handle all 32 HDLC channels at different data rates
using any TDM channel: e.g.
• 16 kbit/s for D-channel signalling
• 64 kbit/s for B-channel signalling
• 8 kbit/s for proprietary signalling (only PB version)
• 256 kbit/s for data transfer in transparent mode.
Data Sheet
TRANSIU in case of TRANSIU interface,
Unit.
118
Functional Description
PEB 20570
PEB 20571
2003-07-31