PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 279

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Figure 71
Note: IREQ is deactivated due to P write operation to OBUSY register. In Motorola
8.6.4
Table 74
Parameter
DU0/DU1 setup time before
DCL falling edge
DU0/DU1 hold time after
DCL falling edge
DRDY setup time before
DCL falling edge
DRDY hold time after DCL
falling edge
DD0/DD1 delay after DCL
rising edge
DD0/DD1 float after DCL
rising edge
1)
Note: FSC and DCL are outputs of the DELIC. Yet, DCL is used also in the DELIC for
Data Sheet
DRDY is sampled only once during every IOM-2 channel, with the first D-bit (D0). For more details refer to
“Support of DRDY Signal from QUAT-S” on Page 103
DSxCS
IREQ
WR
mode DS and CS together time the write access. In Intel mode WR alone times
the write access. For more details regarding the timing required during write
access to the DELIC, refer to section 8.6.2. The other signals required for a write
operation to OBUSY in each mode, are assumed to be driven appropriately.
sampling and driving of the other signals of the IOM-2 interface, and thus the
timing of these signals is related to DCL.
IOM-2 Interface Timing
IREQ Deactivation Timing
IOM-2 Interface Timing
1)
Symbol
t
t
t
t
t
t
UDF
UHF
YDF
YHE
DDE
DFE
Electrical Characteristics and Timing Diagrams
min.
10
10
10
10
7
6
262
Limit Values
typ.
max.
27
22
Unit Notes
ns
ns
ns
ns
ns
ns
Output load
capacity of 50 pF
t
DWI
PEB 20570
PEB 20571
2003-07-31