PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 293

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Note: The frequency of each LCLKn pin (n = 0,1,2,3) should not exceed the maximum
Figure 85
Table 85
Note: Usually CLK_DSP is not used. If it is, special care should be taken regarding it’s
Data Sheet
Parameter
CLK_DSP Maximum
Frequency
CLK_DSP Duty-Cycle
LCLK
frequency, defined according to the GHDLCU operating mode. For more detailes
see section 6.2.6.2 “GHDLC Channel Mode Register”. The Minimum pulse width
(high or low) of LCLK0..3 depends on the DSP clock frequency. Usually this clock
is generated internally by the internal PLL, in a frequency of 61.44 MHz. In this
case the values in the table above are valid. If a lower frequency for DSP-clock is
provided via CLK_DSP input pin, and PDC is used as input, the low/high pulse
width of PDC should not be smaller then 1.5 X DSP-clock-cycle (DSP-clock-cycle
is the cycle time of the provided DSP clock). Usually DSP-clock is generated
internally by the internal PLL, in a frequency of 61.44 MHz. If on the other hand a
lower frequency clcok is provided via CLK_DSP input pin, the frequency of
LCLK0..3 (input or output) should not exceed the frequency of DSP-clock-
frequency / 4 (DSP clcok frequency devided by 4), in order to guarantee a proper
operation of the DELIC.
duty-cycle. The duty-cycle of CLK_DSP should be very close to 50%, since this
clock is also used for the clock-generation for the OAK (phi1, phi2).
0..3
LCLK0..3 Timing in Input Mode
CLK_DSP Input Clock Timing
Symbol
t
t
CMF
CDD
t
LML
Electrical Characteristics and Timing Diagrams
min.
48
Limit Values
276
typ.
max.
61.44 MHz
52
t
Unit Notes
%
LMH
PEB 20570
PEB 20571
2003-07-31