PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 156

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

After the DMA Controller has written the requested number of bytes to the transmit
mailbox, DTXCNT becomes ’F
programmed to cause an interrupt (INT0) to the OAK.
The OAK can now read the data from the transmit mailbox:
- 1st byte in least significant (LS) byte of LS word of the FIFO
- 2nd byte in most significant (MS) byte of LS word of the FIFO, and so on
Note:
1. In case of an odd number of bytes, the last byte is available as the LS byte of the last
2. The OAK reads data word-by-word, exactly like in a non-DMA transfer.
Data Transfer via the Transmit Mailbox - Steps
1. The OAK writes into DTXCNT the number of bytes to be transferred minus one
2. DREQT is asserted (“high” or “low” depending on register MCFG:DRQLV).
3. The DMA asserts DACK = 0 and issues (Tr_Num+1) write transactions to the mailbox
4. DREQT is deasserted (“low” or “high”).
5. If bit DINSTA:TMSK is inactive (“1”), the DMA interrupt (INT0) of the OAK is activated.
6. The OAK reads Tr_Num bytes from the mailbox.
Note: The OAK must not write to the register DTXCNT while the previous DMA transfer
4.10.4
The receive mailbox includes:
• A 16-byte FIFO which the OAK writes into as in 8 regular 16-bit-wide registers and the
• A 4-bit counter for indicating the number of transactions that remain for the transfer
The DELIC initiates all transfers, i.e. each receive is initiated by the OAK. But the
transfers are done by the DMA controller.
When the DELIC receives data e.g. from the GHDLC Unit, the OAK writes this data into
the receive mailbox whereas the 1st byte is put into LS byte of LS word, the 2nd byte into
MS byte of LS word, and so on.
Note: In case of an odd number of bytes, the MS byte of the last word is don’t care.
Then the OAK writes the byte count into register DRXCNT, which causes the assertion
of DREQR (“DMA Request for Receive direction”) pin.
Data Sheet
word while the MS byte of this word is do not care.
(Tr_Num).
(“FIFO”).
DMA controller reads out like from a FIFO (RDT0-7).
(DRXCNT).
has not been finished. (The OAK waits for Transmit DMA Interrupt and tests if
DTXCNT equals ’F
Receive DMA Mailbox
H
’.)
H
’, and DREQT is deasserted. Register DINSTA can be
139
Functional Description
PEB 20570
PEB 20571
2003-07-31