PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 53

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Table 17
Pin
No.
Used for boundary scan according to IEEE 1149.1
54
53
52
51
55
63
Data Sheet
Symbol
TMS
TDI /
SCANEN
TDO
TRST
JTCK
DSP_STOP O
JTAG and Emulation Interface Pins (DELIC-PB)
In (I)
Out (O)
I
I
I
O
I
During
Reset
I
I
I
O
I
BOOT
Strap
(pull-
down)
refer to
Table
19
After
Reset
I
I
I
O
I
O
36
Function
JTAG Test Clock
Provides the clock for JTAG test logic.
Used also for serial emulation interface.
Test Mode Select
A ’0’ to ’1’ transition on this pin is
required to step through the TAP
controller state machine.
Test Data Input
In the appropriate TAP controller state
test data or a instruction is shifted in via
this line.
Used also for serial emulation interface.
This pin must not be driven to low on
the board and should be connected to a
pull-up during reset and operation to
ensure functioning of DELIC
SCAN Enable
When both SCANMO and SCANEN are
asserted, the full-scan tests of DELIC
are activated.
Not used during normal operation.
Test Data Output
In the appropriate TAP controller state
test data or an instruction is shifted out
via this line.
Used also for serial emulation interface.
Test Reset
Provides an asynchronous reset to the
TAP controller state machine.
DSP Stop Pin
Stops external logic during breakpoints.
Activated when a stop to the DSP is
issued.
Pin Description
PEB 20570
PEB 20571
2003-07-31