PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 51

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Table 15
Pin
No.
94
95
1
2
3
48
28
4
90
Data Sheet
Symbol
CLK16-XI
CLK16-XO
DCXOPD
CLK_DSP
DSP_FRQ
L1_CLK
CLKOUT
XCLK
REFCLK
Clock Generator Pins (DELIC-PB) (Additionally to IOM/PCM Clocks)
In (I)
Out (O)
I
O
I
I
I
O
O
I
I/O
During
Reset
I
O
I
I
I
O
O
I
I
After
Reset
I
O
I
I
I
O
O
I
I
34
Function
16.384 MHz External Crystal Input
16.384 MHz External Crystal Output
DCXO Power Down and Bypass
Activating this input powers down the
on-chip DCXO PLL.
The input CLK16-XI is used directly as
the internal 16.384 MHz clock, and the
oscillator and the shaper are bypassed.
Required for testing; during normal
operation this input should be
permanently low (‘0’).
External DSP Clock
Provides a DSP clock other than
61.44 MHz from an external oscillator.
DSP Operational Frequency Selection
(e.g. for test purpose)
0: The DSP is clocked internally at
61.44 MHz
1: The DSP clock is driven by the
CLK_DSP input pin
Layer-1 Clock
15.36 MHz or 7.68 MHz
General Purpose Clock Output
2.048 MHz, 4.096 MHz, 8.192 MHz,
15.36 MHz or 16.384 MHz
External Reference Clock
Synchronization input from Layer-1 ICs
(8 kHz, 512 kHz or 1.536 MHz)
This pin is connected to the VIP’s
REFCLK output at 1.536 MHz.
Reference Clock
Input: Synchronization of DELIC clock
system
Output: Used to drive a fraction of XCLK
to the system clock master
(8 kHz or 512 kHz programmable)
Pin Description
PEB 20570
PEB 20571
2003-07-31